In recent years, miniaturization is required for semiconductor devices which are used as non-volatile storage mediums in, for example, portable electronic devices such as a mobile telephones and integrated circuit memories. For that purpose, a technology to efficiently package a semiconductor chip is required and one such technique to stack semiconductor devices, a package-on-package (pop) technology which has a semiconductor chip mounted on one or more other semiconductor chips, has been developed.
Disclosed in Japanese Patent Application Publication No. JP-A-2003-60121, as a method for manufacturing a semiconductor device, a solder ball is provided on a lower die in a circumference of a semiconductor chip and, as for the solder ball to be pressed via a lead frame, an upper die is joined together. Thereafter, the semiconductor chip, the lead frame and the solder bait are molded to complete the disclosed method for manufacturing the semiconductor device having a part of the solder ball being exposed.
In a semiconductor device having a semiconductor chip mounted, a cost reduction is a consistent issue. For example, in the semiconductor device described in JP-A-2003-60121, a lead frame is used for an internal wiring of the semiconductor device. Further, in a semiconductor device in related art, other than a lead flume, a wiring substrate and such are used. These lead frames, wiring substrates and such are particularly expensive among the materials used for the semiconductor device and occupy a substantial portion of the material cost of the semiconductor device.
Particularly, when stacking semiconductor devices, as lead frames, wiring substrates and such are used in each of the semiconductor devices prior to be stacked, if the number of stacking semiconductor devices is increased, a cost increase is undeniable.